Usb

Pseudo USB SIMULATION

(PROJECT 3)

"ROOT" MODEL:

The "root" in USB is the one that initiates all the transactions, be it input or output transactions. When the root receives a "PACK" , it implies that there is an endpoint at a particular address. Then an acknowledgement signal sent from the endpoint device that consists of data. The corresponding data is displayed on the screen. In the architecture body of the "root" model, two signals called "timer" and "wakeup" are declared. The "wakeup" signal is a pulse signal with 50 percent duty cycle. It basically behaves like a control signal. With the data in the "pack" modified, the root sends a "pin" packet to the endpoint address. The root also sends a "POUT" packet to the endpoint address to check if endpoint has stored the received the data. Then the root waits for a specific time for an acknowledgement "PACK" .Then the returned data is displayed on the terminal.

library ieee;

use ieee.std_logic_1164.all;

library work;

use work.usbpkg.all;

library std;

use std.textio.all;

entity root is

generic (

ADDR : natural := 0

);

port (

signal dport : inout pkt

);

end root;

architecture a of root is

signal timer :boolean;

signal wakeup :boolean;

type boolvec is array (natural range ) of boolean;

...